This disclosure relates generally to the field of computer hardware, and more particularly to a circuit for adjustment of a duty cycle of a clock signal in a computer hardware system.
Electronics and computing systems employ clock signals to control the timing of various components of such systems, such as data transmitters. Modern electronics systems may require clock circuits that operate at very high speeds. High speed input/output links between computers, for example, must conform to standards that may require transmitter speeds above 20 gigabits per second. At such speeds, the duty cycle of the clock signal that controls the components of the electronics system is important. The duty cycle of a clock signal refers to the amount of time a clock signal exhibits a first logic state, for example a logic high, versus the amount of time the clock signal exhibits a second logic state, for example a logic low. A clock signal exhibits a 50% duty cycle if the amount of time that the clock signal exhibits the first logic state is the same as the amount of time the clock signal exhibits the second logic state. Duty cycle distortion is the variance that a particular clock signal exhibits from a desired duty cycle. Duty cycle distortion of a clock signal may cause performance degradation in a high speed electronics system, as many modern electronics systems require a precise clock signal for proper operation. For example, in high-speed data transmission systems, where data is transmitted on both half-cycles of the clock, any clock duty-cycle distortion directly affects the data eye opening and therefore the reliability of the overall system.
For systems that use both the rising and the falling edges of a clock signal for timing, a non-optimal clock signal duty cycle may require a setting the clock signal at a lower clock frequency, reducing system performance. A duty cycle error of just 5% (e.g., from 50% to 45%), for instance, may require a system clock to run at a maximum speed that is up to 10% lower, causing significant impact on system performance. Multi-phase clocking systems often require a symmetrical wave shape that is characteristically desired to operate at 50% duty cycle. However, other applications may require a duty cycle other than 50%. One use of non-50% duty cycle is in digital clocking where pulse-mode latching is used rather than edge-latching, in order to reduce the setup-hold overhead associated with the latches. Actual duty cycles typically do not have precisely the desired value. Even if a clock signal has the required duty cycle at some point in the system, (e.g., at the output of an on-chip voltage controlled oscillator), the duty cycle will deviate from the required percentage as the clock signal is buffered and distributed throughout the chip.